Bulk Fin field-effect transistor (finFET) has become the mainstream complementary metal-oxide semiconductor (CMOS) technology for beyond the 22 nanometer (nm) node. Shallow trench isolation or STI is essential for bulk finFET isolation.
Scaling bulk FinFET requires fin pitch scaling. Fin pitch scaling results in a reduction of STI width and thus the aspect ratio of STI. Filling high aspect ratio STI without voids with dielectric becomes increasingly challenging.
Therefore, there is a need for improved bulk FinFET STI processes.